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An FPGA teaching board: you don't program a processor, you describe a circuit and the chip becomes it.
Each lesson runs your own code on the board. Finish its checks to tick it off.
Build the board in the right order, then power it up and check it, as on the bench.
0 of 9 stepsPull the micro-USB cable and anything on J6. Never work on a live board.
Each fault really happens in the simulation. Trigger one, watch the figure, then read why.
The Basys 3 carries an AMD Artix-7 XC7A35T, an FPGA with 33,280 logic cells and no processor of its own. A Verilog design is turned into wiring inside the chip: an `assign` becomes a gate, an `always @(posedge clk)` becomes flip-flops clocked by the 100 MHz oscillator. Around the FPGA sit the classic Basys parts, all wired straight to its pins: 16 slide switches (up = 1), 16 green LEDs (1 = on), five buttons in a plus (pressed = 1) and a 4-digit display whose segments and digits are both active low, so the digits take turns. Four Pmod ports (JA, JB, JC and the analog JXADC) bring 32 more pins out through 200 Ω resistors. One micro-USB cable powers it, programs it over JTAG and gives you a UART. The FPGA forgets its design at power-off and reloads it from the Quad-SPI flash in under a second, which is when the green DONE LED lights. Everything is 3.3 V: no pin takes 5 V.
| Header | Pin | Name | Functions | Level | Max current | Notes |
|---|---|---|---|---|---|---|
| CLK | W5 | CLK100MHZ(W5) | clk, 100 MHz | 3.3 V | – | The 100 MHz MEMS oscillator IC9. In Vivado: create_clock -period 10.00 on port clk. |
| SW | 0 | SW0(V17) | sw[0] | 3.3 V | – | Slide switch: up connects the pin to 3.3 V, down to GND, through 10 kΩ. Not debounced. |
| SW | 1 | SW1(V16) | sw[1] | 3.3 V | – | Slide switch: up connects the pin to 3.3 V, down to GND, through 10 kΩ. Not debounced. |
| SW | 2 | SW2(W16) | sw[2] | 3.3 V | – | Slide switch: up connects the pin to 3.3 V, down to GND, through 10 kΩ. Not debounced. |
| SW | 3 | SW3(W17) | sw[3] | 3.3 V | – | Slide switch: up connects the pin to 3.3 V, down to GND, through 10 kΩ. Not debounced. |
| SW | 4 | SW4(W15) | sw[4] | 3.3 V | – | Slide switch: up connects the pin to 3.3 V, down to GND, through 10 kΩ. Not debounced. |
| SW | 5 | SW5(V15) | sw[5] | 3.3 V | – | Slide switch: up connects the pin to 3.3 V, down to GND, through 10 kΩ. Not debounced. |
| SW | 6 | SW6(W14) | sw[6] | 3.3 V | – | Slide switch: up connects the pin to 3.3 V, down to GND, through 10 kΩ. Not debounced. |
| SW | 7 | SW7(W13) | sw[7] | 3.3 V | – | Slide switch: up connects the pin to 3.3 V, down to GND, through 10 kΩ. Not debounced. |
| SW | 8 | SW8(V2) | sw[8] | 3.3 V | – | Slide switch: up connects the pin to 3.3 V, down to GND, through 10 kΩ. Not debounced. |
| SW | 9 | SW9(T3) | sw[9] | 3.3 V | – | Slide switch: up connects the pin to 3.3 V, down to GND, through 10 kΩ. Not debounced. |
| SW | 10 | SW10(T2) | sw[10] | 3.3 V | – | Slide switch: up connects the pin to 3.3 V, down to GND, through 10 kΩ. Not debounced. |
| SW | 11 | SW11(R3) | sw[11] | 3.3 V | – | Slide switch: up connects the pin to 3.3 V, down to GND, through 10 kΩ. Not debounced. |
| SW | 12 | SW12(W2) | sw[12] | 3.3 V | – | Slide switch: up connects the pin to 3.3 V, down to GND, through 10 kΩ. Not debounced. |
| SW | 13 | SW13(U1) | sw[13] | 3.3 V | – | Slide switch: up connects the pin to 3.3 V, down to GND, through 10 kΩ. Not debounced. |
| SW | 14 | SW14(T1) | sw[14] | 3.3 V | – | Slide switch: up connects the pin to 3.3 V, down to GND, through 10 kΩ. Not debounced. |
| SW | 15 | SW15(R2) | sw[15] | 3.3 V | – | Slide switch: up connects the pin to 3.3 V, down to GND, through 10 kΩ. Not debounced. |
| LED | 0 | LD0(U16) | led[0] | 3.3 V | 4 mA | Green LED through 330 Ω to GND: 1 lights it, about 4 mA. |
| LED | 1 | LD1(E19) | led[1] | 3.3 V | 4 mA | Green LED through 330 Ω to GND: 1 lights it, about 4 mA. |
| LED | 2 | LD2(U19) | led[2] | 3.3 V | 4 mA | Green LED through 330 Ω to GND: 1 lights it, about 4 mA. |
| LED | 3 | LD3(V19) | led[3] | 3.3 V | 4 mA | Green LED through 330 Ω to GND: 1 lights it, about 4 mA. |
| LED | 4 | LD4(W18) | led[4] | 3.3 V | 4 mA | Green LED through 330 Ω to GND: 1 lights it, about 4 mA. |
| LED | 5 | LD5(U15) | led[5] | 3.3 V | 4 mA | Green LED through 330 Ω to GND: 1 lights it, about 4 mA. |
| LED | 6 | LD6(U14) | led[6] | 3.3 V | 4 mA | Green LED through 330 Ω to GND: 1 lights it, about 4 mA. |
| LED | 7 | LD7(V14) | led[7] | 3.3 V | 4 mA | Green LED through 330 Ω to GND: 1 lights it, about 4 mA. |
| LED | 8 | LD8(V13) | led[8] | 3.3 V | 4 mA | Green LED through 330 Ω to GND: 1 lights it, about 4 mA. |
| LED | 9 | LD9(V3) | led[9] | 3.3 V | 4 mA | Green LED through 330 Ω to GND: 1 lights it, about 4 mA. |
| LED | 10 | LD10(W3) | led[10] | 3.3 V | 4 mA | Green LED through 330 Ω to GND: 1 lights it, about 4 mA. |
| LED | 11 | LD11(U3) | led[11] | 3.3 V | 4 mA | Green LED through 330 Ω to GND: 1 lights it, about 4 mA. |
| LED | 12 | LD12(P3) | led[12] | 3.3 V | 4 mA | Green LED through 330 Ω to GND: 1 lights it, about 4 mA. |
| LED | 13 | LD13(N3) | led[13] | 3.3 V | 4 mA | Green LED through 330 Ω to GND: 1 lights it, about 4 mA. |
| LED | 14 | LD14(P1) | led[14] | 3.3 V | 4 mA | Green LED through 330 Ω to GND: 1 lights it, about 4 mA. |
| LED | 15 | LD15(L1) | led[15] | 3.3 V | 4 mA | Green LED through 330 Ω to GND: 1 lights it, about 4 mA. |
| BTN | U | BTNU(T18) | btnU | 3.3 V | – | Push button to 3.3 V with a 10 kΩ pull-down: reads 1 while pressed. It bounces for a few milliseconds. |
| BTN | L | BTNL(W19) | btnL | 3.3 V | – | Push button to 3.3 V with a 10 kΩ pull-down: reads 1 while pressed. It bounces for a few milliseconds. |
| BTN | C | BTNC(U18) | btnC | 3.3 V | – | Push button to 3.3 V with a 10 kΩ pull-down: reads 1 while pressed. It bounces for a few milliseconds. |
| BTN | R | BTNR(T17) | btnR | 3.3 V | – | Push button to 3.3 V with a 10 kΩ pull-down: reads 1 while pressed. It bounces for a few milliseconds. |
| BTN | D | BTND(U17) | btnD | 3.3 V | – | Push button to 3.3 V with a 10 kΩ pull-down: reads 1 while pressed. It bounces for a few milliseconds. |
| 7SEG | CA | CA(W7) | seg[0], segment a | 3.3 V | – | Segment cathode, shared by all four digits, through 100 Ω: 0 lights the segment. |
| 7SEG | CB | CB(W6) | seg[1], segment b | 3.3 V | – | Segment cathode, shared by all four digits, through 100 Ω: 0 lights the segment. |
| 7SEG | CC | CC(U8) | seg[2], segment c | 3.3 V | – | Segment cathode, shared by all four digits, through 100 Ω: 0 lights the segment. |
| 7SEG | CD | CD(V8) | seg[3], segment d | 3.3 V | – | Segment cathode, shared by all four digits, through 100 Ω: 0 lights the segment. |
| 7SEG | CE | CE(U5) | seg[4], segment e | 3.3 V | – | Segment cathode, shared by all four digits, through 100 Ω: 0 lights the segment. |
| 7SEG | CF | CF(V5) | seg[5], segment f | 3.3 V | – | Segment cathode, shared by all four digits, through 100 Ω: 0 lights the segment. |
| 7SEG | CG | CG(U7) | seg[6], segment g | 3.3 V | – | Segment cathode, shared by all four digits, through 100 Ω: 0 lights the segment. |
| 7SEG | DP | DP(V7) | dp, decimal point | 3.3 V | – | Segment cathode, shared by all four digits, through 100 Ω: 0 lights the segment. |
| 7SEG | AN0 | AN0(U2) | an[0], rightmost digit | 3.3 V | – | Digit anode, through a PNP transistor: 0 turns the digit on. an[0] is the rightmost digit. |
| 7SEG | AN1 | AN1(U4) | an[1], digit 1 | 3.3 V | – | Digit anode, through a PNP transistor: 0 turns the digit on. an[0] is the rightmost digit. |
| 7SEG | AN2 | AN2(V4) | an[2], digit 2 | 3.3 V | – | Digit anode, through a PNP transistor: 0 turns the digit on. an[0] is the rightmost digit. |
| 7SEG | AN3 | AN3(W4) | an[3], leftmost digit | 3.3 V | – | Digit anode, through a PNP transistor: 0 turns the digit on. an[0] is the rightmost digit. |
| JA | 1 | JA1(J1) | JA[0] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JA | 2 | JA2(L2) | JA[1] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JA | 3 | JA3(J2) | JA[2] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JA | 4 | JA4(G2) | JA[3] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JA | 5 | GND | – | – | – | |
| JA | 6 | 3V3 | 3.3 V out | 3.3 V | 1,000 mA | The 3.3 V rail, shared by all Pmods: up to 1 A in total. |
| JA | 7 | JA7(H1) | JA[4] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JA | 8 | JA8(K2) | JA[5] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JA | 9 | JA9(H2) | JA[6] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JA | 10 | JA10(G3) | JA[7] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JA | 11 | GND | – | – | – | |
| JA | 12 | 3V3 | 3.3 V out | 3.3 V | 1,000 mA | The 3.3 V rail, shared by all Pmods: up to 1 A in total. |
| JB | 1 | JB1(A14) | JB[0] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JB | 2 | JB2(A16) | JB[1] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JB | 3 | JB3(B15) | JB[2] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JB | 4 | JB4(B16) | JB[3] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JB | 5 | GND | – | – | – | |
| JB | 6 | 3V3 | 3.3 V out | 3.3 V | 1,000 mA | The 3.3 V rail, shared by all Pmods: up to 1 A in total. |
| JB | 7 | JB7(A15) | JB[4] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JB | 8 | JB8(A17) | JB[5] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JB | 9 | JB9(C15) | JB[6] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JB | 10 | JB10(C16) | JB[7] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JB | 11 | GND | – | – | – | |
| JB | 12 | 3V3 | 3.3 V out | 3.3 V | 1,000 mA | The 3.3 V rail, shared by all Pmods: up to 1 A in total. |
| JC | 1 | JC1(K17) | JC[0] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JC | 2 | JC2(M18) | JC[1] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JC | 3 | JC3(N17) | JC[2] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JC | 4 | JC4(P18) | JC[3] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JC | 5 | GND | – | – | – | |
| JC | 6 | 3V3 | 3.3 V out | 3.3 V | 1,000 mA | The 3.3 V rail, shared by all Pmods: up to 1 A in total. |
| JC | 7 | JC7(L17) | JC[4] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JC | 8 | JC8(M19) | JC[5] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JC | 9 | JC9(P17) | JC[6] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JC | 10 | JC10(R18) | JC[7] | 3.3 V | 16 mA | Pmod signal, straight to an FPGA pin through 200 Ω on the board. 3.3 V only. |
| JC | 11 | GND | – | – | – | |
| JC | 12 | 3V3 | 3.3 V out | 3.3 V | 1,000 mA | The 3.3 V rail, shared by all Pmods: up to 1 A in total. |
| JXADC | 1 | XA1_P(J3) | JXADC[0], VAUX6P | 3.3 V | – | Digital I/O through 100 Ω, or an analog input pair for the XADC (0-1 V). |
| JXADC | 2 | XA2_P(L3) | JXADC[1], VAUX14P | 3.3 V | – | Digital I/O through 100 Ω, or an analog input pair for the XADC (0-1 V). |
| JXADC | 3 | XA3_P(M2) | JXADC[2], VAUX7P | 3.3 V | – | Digital I/O through 100 Ω, or an analog input pair for the XADC (0-1 V). |
| JXADC | 4 | XA4_P(N2) | JXADC[3], VAUX15P | 3.3 V | – | Digital I/O through 100 Ω, or an analog input pair for the XADC (0-1 V). |
| JXADC | 5 | GND | – | – | – | |
| JXADC | 6 | 3V3 | 3.3 V out | 3.3 V | 1,000 mA | The 3.3 V rail, shared by all Pmods: up to 1 A in total. |
| JXADC | 7 | XA1_N(K3) | JXADC[4], VAUX6N | 3.3 V | – | Digital I/O through 100 Ω, or an analog input pair for the XADC (0-1 V). |
| JXADC | 8 | XA2_N(M3) | JXADC[5], VAUX14N | 3.3 V | – | Digital I/O through 100 Ω, or an analog input pair for the XADC (0-1 V). |
| JXADC | 9 | XA3_N(M1) | JXADC[6], VAUX7N | 3.3 V | – | Digital I/O through 100 Ω, or an analog input pair for the XADC (0-1 V). |
| JXADC | 10 | XA4_N(N1) | JXADC[7], VAUX15N | 3.3 V | – | Digital I/O through 100 Ω, or an analog input pair for the XADC (0-1 V). |
| JXADC | 11 | GND | – | – | – | |
| JXADC | 12 | 3V3 | 3.3 V out | 3.3 V | 1,000 mA | The 3.3 V rail, shared by all Pmods: up to 1 A in total. |
| UART | RX | RsRx(B18) | RsRx, UART in, from the PC | 3.3 V | – | The USB-UART through the FT2232HQ. Names are from the PC's side: RsRx is the FPGA's input. |
| UART | TX | RsTx(A18) | RsTx, UART out, to the PC | 3.3 V | – | The USB-UART through the FT2232HQ. Names are from the PC's side: RsRx is the FPGA's input. |
| VGA | vgaRed0 | vgaRed[0](G19) | vgaRed[0] | 3.3 V | – | 4-bit resistor DAC per colour into the monitor's 75 Ω; Hsync and Vsync through 100 Ω. |
| VGA | vgaRed1 | vgaRed[1](H19) | vgaRed[1] | 3.3 V | – | 4-bit resistor DAC per colour into the monitor's 75 Ω; Hsync and Vsync through 100 Ω. |
| VGA | vgaRed2 | vgaRed[2](J19) | vgaRed[2] | 3.3 V | – | 4-bit resistor DAC per colour into the monitor's 75 Ω; Hsync and Vsync through 100 Ω. |
| VGA | vgaRed3 | vgaRed[3](N19) | vgaRed[3] | 3.3 V | – | 4-bit resistor DAC per colour into the monitor's 75 Ω; Hsync and Vsync through 100 Ω. |
| VGA | vgaGreen0 | vgaGreen[0](J17) | vgaGreen[0] | 3.3 V | – | 4-bit resistor DAC per colour into the monitor's 75 Ω; Hsync and Vsync through 100 Ω. |
| VGA | vgaGreen1 | vgaGreen[1](H17) | vgaGreen[1] | 3.3 V | – | 4-bit resistor DAC per colour into the monitor's 75 Ω; Hsync and Vsync through 100 Ω. |
| VGA | vgaGreen2 | vgaGreen[2](G17) | vgaGreen[2] | 3.3 V | – | 4-bit resistor DAC per colour into the monitor's 75 Ω; Hsync and Vsync through 100 Ω. |
| VGA | vgaGreen3 | vgaGreen[3](D17) | vgaGreen[3] | 3.3 V | – | 4-bit resistor DAC per colour into the monitor's 75 Ω; Hsync and Vsync through 100 Ω. |
| VGA | vgaBlue0 | vgaBlue[0](N18) | vgaBlue[0] | 3.3 V | – | 4-bit resistor DAC per colour into the monitor's 75 Ω; Hsync and Vsync through 100 Ω. |
| VGA | vgaBlue1 | vgaBlue[1](L18) | vgaBlue[1] | 3.3 V | – | 4-bit resistor DAC per colour into the monitor's 75 Ω; Hsync and Vsync through 100 Ω. |
| VGA | vgaBlue2 | vgaBlue[2](K18) | vgaBlue[2] | 3.3 V | – | 4-bit resistor DAC per colour into the monitor's 75 Ω; Hsync and Vsync through 100 Ω. |
| VGA | vgaBlue3 | vgaBlue[3](J18) | vgaBlue[3] | 3.3 V | – | 4-bit resistor DAC per colour into the monitor's 75 Ω; Hsync and Vsync through 100 Ω. |
| VGA | HS | Hsync(P19) | Hsync | 3.3 V | – | 4-bit resistor DAC per colour into the monitor's 75 Ω; Hsync and Vsync through 100 Ω. |
| VGA | VS | Vsync(R19) | Vsync | 3.3 V | – | 4-bit resistor DAC per colour into the monitor's 75 Ω; Hsync and Vsync through 100 Ω. |
| PS2 | CLK | PS2Clk(C17) | PS2Clk, PULLUP true | 3.3 V | – | Keyboard or mouse from the USB host chip, as PS/2. Needs PULLUP true in the constraints. |
| PS2 | DATA | PS2Data(B17) | PS2Data, PULLUP true | 3.3 V | – | Keyboard or mouse from the USB host chip, as PS/2. Needs PULLUP true in the constraints. |
| J6 | 1 | EXT | 4.5-5.5 V in | 5 V | – | External 4.5-5.5 V input. No reverse diode, no fuse; JP2 must be on EXT to use it. |
| J6 | 2 | GND | – | – | – |
Sensors and actuators this board drives, with the real connections.
Anode to JB pin 1 through 220 Ω, cathode to a Pmod GND pin. Drive it from your design like any LED.
| Part pin | Board pin |
|---|---|
| A | JB1Wire colour orange |
| K | GNDWire colour black |
The board already adds 200 Ω in series, so the LED stays dim but safe even without your resistor; never feed a Pmod pin from 5 V.
Between JB pin 2 and GND. Add PULLUP true for that pin in the constraints so it reads 1 until pressed, and debounce it in your design.
| Part pin | Board pin |
|---|---|
| 1 | JB2Wire colour blue |
| 3 | GNDWire colour black |
+ to JB pin 3. Toggle the pin at an audible rate (count CLK_HZ / (2 × f) cycles per half period) to play a note.
| Part pin | Board pin |
|---|---|
| + | JB3Wire colour orange |
| − | GNDWire colour black |
3.3 V and GND from a Pmod, SCL to JC pin 1, SDA to JC pin 2.
| Part pin | Board pin |
|---|---|
| VCC | 3V3Wire colour red |
| GND | GNDWire colour black |
| SCL | JC1Wire colour yellow |
| SDA | JC2Wire colour blue |
There is no I2C peripheral: your design needs an I2C master (open-drain outputs and pull-ups in the constraints).
3.3 V and GND from a Pmod, SCL to JC pin 1, SDA to JC pin 2.
| Part pin | Board pin |
|---|---|
| GND | GNDWire colour black |
| VCC | 3V3Wire colour red |
| SCL | JC1Wire colour yellow |
| SDA | JC2Wire colour blue |
Your design must send the display's I2C setup commands and pixel data itself; that is a big project, not a first one.