Lesson 2 of 5

Blink with a counter

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// Blink: count clock cycles and flip LD0 every half period. module top #( parameter CLK_HZ = 100_000_000, // the board clock: cycles per second parameter BLINK_HZ = 2 ) ( input clk, // W5 output reg [15:0] led ); // Clock cycles in half a blink. localparam HALF = CLK_HZ / (2 * BLINK_HZ); reg [31:0] count = 0; initial led = 16'b0; always @(posedge clk) begin if (count == HALF - 1) begin count <= 0; led[0] <= ~led[0]; // flip LD0 if (led[0]) led[15:12] <= led[15:12] + 1; // LD0 is about to go off: one more blink end else begin count <= count + 1; end end endmodule

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Nothing printed yet. Press Run.

An FPGA has no delay(). To blink LD0 you count clock cycles: 100 million of them make a second.

Sequential logic with always @(posedge clk)
Time from counting, not waiting
Set the blink rate with a chip

iynk runs your Verilog as a behavioural model, cycle by cycle on the board clock. It does not synthesise, place or route: no timing, no LUT counts.

Pin	Connects to	What it does
`CLK100MHZ`	100 MHz oscillator IC9 → pin W5	Every rising edge updates the registers
`LD0`	FPGA pin U16 (led[0])	Changes state every HALF cycles
`LD12`	FPGA pin P3 (led[12])	Lowest bit of the blink count

Wire it in

Sensors and actuators this board drives, with the real connections.

All 5 parts on the Digilent Basys 3 page

Blink with a counter

Try it yourself

Serial monitor

Checks

Break it

Parameters

Wire it in

Blink with a counter

Try it yourself

Serial monitor

Checks

Break it

Parameters

Wire it in